The present disclosure relates to a counter control signal generating circuit, and more particularly to a counter control signal generating circuit capable of preventing current consumption caused by a column address strobe (CAS) latency counter unnecessarily operating during a read operation.
In memory devices of a double data rate 2 (DDR2) SDRAM grade or higher, a new concept of additive latency (AL) and write latency (WL) has been introduced. In accordance with this concept, WL is defined to be equal to “AL+CAS latency (CL)−1”, and read latency (RL) is defined to be equal to “AL+CL”.
On the other hand, when viewing at the side receiving an external address, RL is defined to be equal to AL because CL in a read operation is undertaken at the side of a data output stage.
The introduction of AL and WL is advantageous in that the input positions of read or write commands can be more freely determined. However, a drawback also occurs due to the newly introduced AL and WL. The drawback is an increase in current consumption caused by a CL counter operating to control the AL and WL.
In order to reduce the current consumption, a current consumption reduction scheme has been proposed in which the operation of the counter is stopped when read or write operation cannot be carried out, that is, when all banks are in a precharged state, namely, in an idle state. However, this scheme still has a problem of a current consumption caused by an unnecessary operation of the CL counter carried out during a read operation.
Accordingly, in order to prevent the current consumption caused by the unnecessary operation of the CL counter during the read operation, a read-write address generating circuit has been developed which is capable of stopping an operation of the CL counter when a read command is input.
FIG. 1A is a block diagram illustrating a configuration of a conventional read-write address generating circuit.
The conventional read-write address generating circuit includes an address latch unit (Address Latch Block) A1 for receiving an external address signal Address, and outputting a latched address signal Latched RDWT Address in synchronism with a read or write command RDWT, an AL counter (AL Count Block) A2 for receiving the latched address signal Latched RDWT Address, and outputting an AL counted address signal AL Counted Address counted in accordance with a predetermined AL, in synchronism with a count clock signal Count Clock and an AL signal AL, and a read address generator (Read Control Block) A3 for receiving the AL counted address signal AL Counted Address, and generating a read address signal Read Address for an actual read operation. The circuit also includes a counter control signal generator (CL_Count_Clock Control) A4 for receiving a read recognition signal IRD, which is enabled in accordance with a read command, an internal clock signal ICLK, which is an internal count clock having the same period as an external clock, and generating a counter control signal CL_Count_Clock for controlling operation of a CL counter (CL Count Block) A5. The CL counter A5, which is also included in the circuit, receives the AL counted address signal AL Counted Address, and outputs a CL counted address signal CL Counted Address counted in accordance with a predetermined CL, in synchronism with a CL signal CL, and a write address generator (Write Control Block) A6 for receiving the CL counted address signal CL Counted Address, and generating a write addressing signal Write Address for an actual write operation.
Hereinafter, operation of the counter control signal generator (CL_Count_Clock Control) A4 will be described in detail with reference to FIG. 1B. First, when the write recognition signal WT is enabled, namely, is transited to a high level, in accordance with a write command, an enable signal CLKCTL is transited to a high level, thereby causing a NAND gate NDA3 to operate as an inverter. As a result, the counter control signal CL_Count_Clock is assumed an inverted signal of the internal clock signal ICLK, so that it is enabled. Accordingly, the CL counter (CL Count Block) A5 operates. On the other hand, when the read recognition signal IRD is enabled, namely, is transited to a high level, in accordance with a read command, an enable signal CLKCTL is transited to a low level. As a result, the counter control signal CL_Count_Clock is transited to a high level, namely, a disable state. Accordingly, the operation of the CL counter (CL Count Block) A5 is stopped. Thus, the counter control signal generator (CL_Count_Clock Control) A4 prevents current consumption caused by an unnecessary operation of the CL counter (CL Count Block) A5 carried out during a read operation by generating a counter control signal CL_Count_Clock enabled in response to a write command, and disabled in response to a read command.
In the above-mentioned read-write address generating circuit, however, an internal problem may occur in accordance with AL. This will be described with reference to FIG. 1C depicting a timing diagram of internal signals of the counter control signal generator.
When it is assumed that burst length (BL) is 4, as shown in FIG. 1C, a write command may be generated after a period of 4 clocks has elapsed from generation of a read command RD(2). On the other hand, a read recognition signal IRD, which disables the counter control signal CL_Count_Clock, is generated after a delay period corresponding to an AL has elapsed from the generation of the read command. In this case, if the AL is 4, the enable period of the read recognition signal IRD generated in accordance with the read command RD(2) may overlap with the enable period of a write recognition signal WT generated in accordance with a write command WT (3), as indicated by a circle a in FIG. 1C. As a result, as indicated by a block b in FIG. 1C, the enable period of the counter control signal CL_Count_Clock may be terminated after one clock. In this case, there is a problem in that it may be impossible to completely receive a write address.